Cover -- Title Page -- Copyright Page -- Dedication -- PREFACE -- THE AUTHORS -- Table of Contents -- 1: Real-Time Expert Systems -- 1.1 Expert Systems -- 1.2 Real-Time Systems -- 1.3 Why Real-Time Expert System? -- 1.4 Existing Architectures -- 1.4.1 von Neumann Architectures -- 1.4.2 Dataflow Architectures -- 1.4.3 Multiprocessor Systems -- 1.5 Systems Requirements -- 1.5.1 Timing -- 1.5.2 Procedural & Declarative Representations -- 1.5.3 Uncertainty -- 1.5.4 Environment Interface -- 1.5.5 Hierarchical Organization -- 1.6 Summary -- 2: System Design -- 2.1 Topology -- 2.2 Processor Structure -- 2.2.1 Interference Mechanism -- 2.2.2 Dataflow Methodology -- 2.2.3 Priority -- 2.2.4 Uncertainty Processing -- 2.2.5 External Interface -- 2.2.6 Temporal Data -- 2.2.7 Procedural Data -- 2.2.8 Communication -- 2.2.9 Dynamic Memories -- 2.3 Summary -- 3: System Implementation -- 3.1 ARL Implementation -- 3.1.1 ARL Control -- 3.1.2 ARL Interfaces -- 3.1.3 Memory Address Hardware -- 3.1.4 Rule Memory -- 3.1.5 ARL Memory -- 3.1.6 Memory Register -- 3.1.7 Decrement Logic -- 3.1.8 Link Priority Logic -- 3.1.9 Negation Logic -- 3.1.10 Min/Max Logic -- 3.1.11 ARL Microcode -- 3.2 APQ Implementation -- 3.2.1 APQ Control -- 3.2.2 APQ Interfaces -- 3.2.3 APQ Priority Logic -- 3.2.4 APQ Memory Organization -- 3.2.5 APQ Register File -- 3.2.6 APQ Free Register and Pointer Buffer -- 3.2.7 APQ Empty Queue Logic -- 3.2.8 APQ Microcode -- 3.3. CPQ Implementation -- 3.3.1 CPQ Microcode -- 3.4 AP Implementation -- 3.4.1 AP Control -- 3.4.2 AP Interfaces -- 3.4.3 Antecedent Memory -- 3.4.4 Antecedent Compare Hardware -- 3.4.5 Wait List Memory -- 3.4.6 AP Microcode -- 3.5 CP Implementation -- 3.5.1 CP Code -- 3.6 WM Implementation -- 3.7 Message Buffer Implementation -- 3.8 External Interface Implementation -- 3.9 Real-Time Clock Implementation